- We have run this process for customers using their design and incorporating our test structure for test verification.
- Aluminum and Tungsten gate metals have been processed - others are possible.
- Our Vt's are well matched but implant splits are possible.
- Typical run time is ~8 weeks
Details about the SMFL CMOS Process, Performance, Specifications, and Options
If you require this information or a quote on your process, please contact T. Grimsley